The present invention relates to an arithmetic circuit and, more particularly, to an arithmetic circuit for calculating and accumulating the absolute values of the difference between two numerical values.
Calculating and accumulating the absolute values of the difference between two numerical values is commonly practiced to, for example, search for an optimum block in the event of coding a video signal using motion compensation. An arithmetic circuit for implementing this kind of operation has customarily been made up of an absolute value calculating section and an accumulating section. The absolute value calculating section or calculator inverts one of two n-bit numerical values represented by 2's compliment notation, adds the inverted numerical value to the other numerical value, and processes the sum on the basis of the sign so as to produce the absolute value of the difference. The accumulating section or accumulator sequentially accumulates the resulting absolute values of the difference. The absolute value calculator may be implemented with an absolute value calculating circuit which is disclosed in European patent application EP 0328063 A2 laid open for public inspection on Aug. 16, 1989. On the other hand, the accumulator may be constituted by the combination of an adder and a delay circuit. Such a conventional arithmetic circuit is advantageous in that the absolute value calculator needs only a single adder. However, the conventional circuit cannot avoid being a large scale circuit which not only slows down the operation due to the delay in data propagation but also aggravates power consumption.